The present invention relates to a nonvolatile read only memory device.
A nonvolatile read only memory (abbreviated as ROM) has dominantly used for memory devices for storing programs in electronic computers and fixed data.
A prior ROM will be described with reference to FIGS. 1 and 2. In FIG. 1 illustrating a circuit diagram of a prior ROM, the ROM includes a MOS transistor (referred to as a memory cell transistor) having an N-channel dual gate structure formed on a P substrate and serving as a memory cell. The memory cell transistor 10 has a channel length of 2.5 .mu.m, and a threshold value of 1.4 V. The transistor 10 is one of the memory cell transistors forming a memory array. The memory cell transistor 10 is connected at the gate to a row decoder 12 through a word line 13, at the source to a ground potential point 14, and at the drain to a digit line 16 connected to the drains of other memory cell transistors (not shown). The digit line 16 is connected through an enhancement type (referred to as E-type) transistor 18 to a first bias circuit 20. The gate of the transistor 18, connected to a column selection line 22 connected to a column decoder, receives a column selection signal.
The gate of a MOS transistor of the dual gate structure for a reference potential generation (referred to as a reference cell transistor) is connected to a node between transistors 26 and 28 of the depletion type(referred to as D-type). A channel length of a reference cell transistor 24 is 2.5 .mu.m and a threshold voltage thereof is 1.4 V. The source of the transistor 26 is connected to the ground potential point 14 and a power source voltage Vcc of 5 V, for example, is supplied to the drain of the transistor 28. Accordingly, the potential at the node 30 corresponds to the one formed by resistor-division of the potential Vcc through the transistors 26 and 28.
The reference cell transistor 24 is connected at the source to the ground potential point 14 and at the drain to a second bias circuit 34 through an E-type transistor 32 which is supplied at the gate with the power source voltage Vcc. Accordingly, the reference potential generated by the reference cell transistor 24 is supplied through the transistor 32 to the second bias circuit 34. The output signal V11 generated by the first bias circuit 20 and the output signal V21 by the second bias circuit 34 are applied to a differential amplifier 36. The output signal from the differential amplifier 36 is applied to an amplifier 38 which in turn produces output signals V12 and V22. The threshold voltage of each of the E-type transistors 18 and 32 is 0.7 V, and the threshold voltage of each of the D-type transistors 26 and 28 is -3.0 V.
The operation of the circuit as mentioned above will be described. For selecting a specific memory cell transistor, for example, the memory cell transistor 10, in the memory array, the potential of the output signal from the row decoder 12 and on the column select line 22 is set at a high level of approximately 5 V. At this time, the potential V11 on the output line 40 of the first bias circuit 20 is determined due to a conductance ratio of the first bias circuit 20 and the memory cell transistor 10. When the memory cell transistor 10 is in a non-write mode the conductance of the memory cell transistor 10 is large, so that the potential V11 is at a low level. On the other hand, when the memory cell transistor 10 is in a write mode, the conductance of the memory cell transistor 10 is small, so that the potential V11 is at a high level.
The potential V21 on the output line 42 from the second bias circuit 34 is likewise determined by a conductance ratio of the second bias circuit 34 and the reference cell transistor 24. It is assumed that the memory cell transistor 10 and the reference cell transistor 24 are manufactured by the same process, and with the same dimension. The power source voltage of 5 V is applied to the gate of the memory cell transistor 28 and a voltage of 3 V, for example, which is dropped by the D-type transistor 28, is applied to the gate of the reference cell transistor 24. Accordingly, the potential on the output line 42 from the second bias circuit 34 is between high and low levels of the potential V11 appearing on the output line 40 from the first bias circuit 20.
A difference potential between the output potentials V11 and V21 is detected by the differential amplifier 36. The difference potential is amplified by the amplifier 38 and the amplifier 38 produces digital signals V12 and V22 on the output lines 44 and 46. When the potential V11 on the output line 40 from the first bias circuit 20 is logical "0", for example, the digital signals V12 and V22 are logical "1" and "0", respectively.
Normally, the output signal from the row decoder 12 is proportional to the power source voltage Vcc. If, assuming that an amount of data written in the memory cell transistor 10 (referred to as a data write amount) is .DELTA.Vth and the threshold voltage of the transistor 10 in a non-write mode is Vtc, the current through the transistor 10 is proportional to (Vcc-.DELTA.Vth-Vtc). The gate potential of the reference cell transistor 24 is approximately Vcc-.alpha.. .alpha. is determined by the conductance ratio of the D-type transistors 26 and 28.
If the reference cell transistor 24 has much the same dimension as that of the memory cell transistor 10, the threshold voltage of the reference cell transistor 24 is equal to that Vtc of the memory cell transistor 10 in a non-write mode. Therefore, the current flowing through the reference cell transistor 24 is proportional to Vcc-.alpha.-Vtc. When the current of the reference cell transistor 24 is larger than that of the memory cell transistor 24 in a write mode, the following relation holds EQU Vcc-.DELTA.Vth-Vtc&lt;Vcc-.alpha.-Vtc
Hence, EQU .DELTA.Vth&gt;.alpha.
When the write amount in the memory cell transistor 10 is larger than .alpha., the output potential V11 of the first bias circuit 20 is higher than the output potential V21 of the second bias circuit 34. The digital signal V12 generated by the amplifier 38 is low in level, independently of the power source voltage.
FIG. 2 shows a relationship between the power source voltage Vcc and the output potential V12 of the amplifier 38. In the figure, .beta. designates a relationship when no data is written into the memory cell transistor 10 (.DELTA.Vth=0) and .gamma. designates a relationship when .DELTA.Vth&gt;.alpha.. In a practical power voltage range, when .DELTA.Vth=0, the output potential V12 is high level. When .DELTA.Vth&gt;.alpha., the output potential V12 is low in level. Normally, the ROM is used under the condition given by the curves .beta. and .gamma..
A curve .delta. designates a relationship when 0&lt;.DELTA.Vth&lt;.alpha.. The data write amount in the memory cell transistor 10 changes with time, so that 0&lt;.DELTA.Vth&lt;.alpha. is satisfied. In this state, when the power source voltage Vcc is increased, the output potential V12 of the amplifier 38 changes from high level into low level at a certain power source voltage Vcc. Therefore, a change in the write amount of the memory cell transistor 10 can be detected.
On the other hand, in the case of the curve .gamma. which satisfies the relationship .DELTA.Vth&gt;.alpha., the output potential V12 of the amplifier 38 exhibits no change, even if the power source voltage Vcc is changed. Therefore, a time variation of the write amount can not be detected. In the nonvolatile read only memory, it is desirable to check at a desired time a time variation of the memory contents once stored, for the purpose of checking the reliability of the ROM.
A ROM similar to the above-mentioned ROM is disclosed in Japanese patent publication (KOKAI) 2No. 51-94729.